Project Name: PCI bridge

Introduction | Documentation | Characteristics | Current Status | To Do list | Test Application | Download | Testbench | References | Links | Mailing list | Contacts

To Do list

PCI Behavioral Models and PCI bus Monitor

We start using the PCI BFMs written by Blue Beaver. This BFMs support only MEMORY READ/WRITE and CONFIG READ/WRITE commands.

Synchronous clock operation

There should be added one more DEFINE for synchronous clock operation between PCI and WISHBONE buses. This is usefull in FPGAs to use less slices when an application does not require different bus clock domains.

Design document

After finishing the testbench, we will write the design document describing the PCI core structure and all defines that can be (an why) changed by an user.