Project Name: PCI bridge

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Supported targets

We prepared PCI bridge core to be implemented into the Xilinx FPGA (tested on Spartan II). Now we are preparing it for ASIC. Artisan memory blocks are already prepared.

Size in FPGAs

We implement PCI bridge into Spartan II 150 Kgates -5 speed grade. We used 2 base addresses for accessing the WISHBONE bus from PCI side and 2 base addresses for accessing the PCI bus from WISHBONE side. We used 6 Block Select+ RAMs for FIFOs and all synchronization for two clock domains. PCI bridge also consists all Image and Control registers beside PCI Header. With all these features PCI bridge occupies about 1300 Xilinx FPGA slices (76% of Spartan II 150).

This will be updated soon for other FPGAs.