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Introduction

The aim of this project is to define the basic OpenRISC 1000 architecture and to add improvements and extensions in the future.

OpenRISC 1000 is architecture for a family of free, open source RISC processor cores. As an architecture, OpenRISC 1000 allows for a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. It is a 32/64-bit load and store RISC architecture designed with emphasis on performance, simplicity, low power requirements, scalability and versatility. OpenRISC 1000 architecture targets medium and high performance networking, embedded, automotive and portable computer environments.

Performance features include fully 32/64-bit architecture, vector, DSP and floating-point instructions, powerful virtual memory support, cache coherency, optional SMP and SMT support and support for fast context switching. Architecture defines several features for networking and embedded computer environments. Most notable are several instruction extensions, configurable number of general-purpose registers, configurable cache and TLB sizes, dynamic power management support and space for user provided instructions. OpenRISC 1000 architecture is a predecessor of more powerful and richful next generation OpenRISC architectures.

Features

OpenRISC 1000 architecture includes the following principal features:

• A completely open and free architecture
• A linear, 32-bit or 64-bit logical address space with implementation specific physical address space
• Simple and uniform-length instruction formats featuring different instruction set extensions:
  • OpenRISC Basic Instruction Set (ORBIS32/64) with 32 bits wide instructions aligned on 32-bit boundaries in memory and operating on 32 bits and 64 bits data
  • OpenRISC Vector/DSP eXtension (ORVDX64) with 32 bits wide instructions aligned on 32-bit boundaries in memory and operating on 8, 16, 32 and 64 bits data
  • OpenRISC Floating-Point eXtension (ORFPX32/64) with 32 bits wide instructions aligned on 32-bit boundaries in memory and operating on 32 bits and 64 bits data
• Two simple memory addressing modes where memory address is calculated with:
  • Addition of register operand and signed 16-bit immediate
  • Addition of register operand and signed 16-bit immediate followed by update ofregister operand with calculated effective address
• Most instructions operate on two register operands (or one register and a constant), and place the result in a third register
• Shadowed or single 32-entry or narrow 16-entry general purpose register file
• Branch delay slot for keeping pipeline as full as possible

Status

• Basic architecture is defined in OpenRISC 1000 Architecture Manual and is not being changed anymore
• For architecture evaluation and software development an architecture simulator is available. See or1ksim page
• First implementation is available. See OR1200 page

Documentation

Latest OpenRISC architecture manual is available from the OpenCores CVS under module name or1k/docs:

• OpenRISC 1000 Architecture Manual (PDF, 1.4MB)
• OpenRISC 1000 Architecture Manual (MS Word, 3.8MB)

Wish List (TODO List)

This is a what we want to do/have in the future and right now nobody is working on this. If you want to help, send an email to the mailing list.

• Native english speaker needs to go through the OpenRISC Architecture document and correct it [Bob Gardner is working on this one]
• Promotion of the OpenRISC architecture

Past Contributors

These are the people currently not working on the OpenRISC, but have contributed in the past:

• Johan Rydberg, jrydberg@opencores.org_NOSPAM
• Chen-Min Chen, jimmy@opencores.org_NOSPAM
• Greg McGary, greg@mcgary.org_NOSPAM
• Chris Ziomkowsi, chris@opencores.org_NOSPAM

Current Developer(s)

The team working on the OpenRISC architecture:

• Marko Mlinar, markom@opencores.org_NOSPAM
• Simon Srot, simons@opencores.org_NOSPAM
• Matan Ziv-Av, matan@opencores.org_NOSPAM
• Damjan Lampret, lampret@opencores.org_NOSPAM

Mailing list / Discussion Forum

To participate in the development or simply to discuss OR1K architecture issues, go to the openrisc mailing list. To subscribe to the list, follow mailing list subscribe instructions.

Page Maintainer

This web page is maintained by Damjan Lampret.